The present invention generally relates to semiconductor processing, and in particular to a method and system for evaluating new product masks that includes detecting defects on a reticle containing the new product mask and evaluating the yield impact of such defects.
In the semiconductor industry, there is a continuing trend toward higher device densities and smaller device dimensions, which requires new product masks with ever smaller and ever more precise details. Producing a high yield of wafers with such higher densities and smaller dimensions through such new product masks depends, at least in part, on the manufacturing process window achieved during the processing of different lithography layers. Such process window depends in turn, at least in part, on defects on reticles employed in producing a wafer. Such reticle defects can include xe2x80x9csoftxe2x80x9d reticle defects, which lead to marginal printing. With the increasing use of advanced reticle enhancement techniques, the effect of defects, even soft reticle defects in new product masks, can be magnified when transferred to a wafer.
Conventionally, early in the wafer production process, lithography quality assurance engineers will run test wafers with focus exposure matrices to determine lithography process windows. Later in the wafer production process, development quality assurance personnel may run critical dimension (CD) splits at key layers to determine how variations are affecting the product performance. But each of these techniques suffer from drawbacks. For example, undersized contacts resulting from either repair, chrome defect or particle problems may not be detected, particularly when die-to-die comparisons are not available.
Analyzing a focus exposure matrix (FEM) on flat test wafers that have not been exposed to other topography influencing processes (e.g., deposition, etching) may not account for problems experienced due to such topography, and may similarly not account for interactions with non-lithography modules. Similarly, examining a critical dimension (CD) split exposes but a part of the lithography process space, and may leave certain defects undetected. Thus, some reticle defects associated with new product masks may not be detected using these conventional methods. Further, even if a reticle defect is detected using these conventional methods, analyses concerning the effects, if any, on the production yield may not be performed, and thus manufacturing, repairing, and/or scrapping decisions may be made. Thus, a method for evaluating new products masks, which includes detecting reticle defects and predicting the effect of such reticle defects on production yields of wafers printed using such a defective reticle is still required.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for printing Focus Exposure Matrices (FEMs) on full flow production wafers as part of a hierarchy of Quality Assurance (QA) testing. FEMs can be formed from a plurality of patterns created with varying resist exposure dosages and stepper focuses. Thus, pattern shapes and/or line widths in the FEMs can vary within one wafer, which facilitates collecting data suitable for comparison analysis. Printing and analyzing such FEMs facilitates evaluating new product masks by facilitating detecting reticle defects and predicting product yields when a reticle with detected defects is employed to print wafers. The full flow production wafers, (printed by the reticle containing the new product mask being evaluated), upon which the FEMs are printed at one or more different processing steps, are subjected, in addition, to end of line electrical testing, critical dimension measurement and analysis. The reticle is also subjected to a defect scan and a reticle scan that in turn lead to a printability simulation. Thus, reticle defects which may not be detected by conventional systems can be located, and analysis concerning the effects, if any, on production yield are facilitated.
At least two hurdles exist in evaluating a new product mask: detecting errors on the reticle and understanding the yield impact of defects. Lithography engineers employ reticle inspection tools to detect the existence of reticle defects. In the mask shop, reticle scans coupled with printability simulations can be employed to acquire first data. Then, in the Fab, engineers may employ automated defect inspection tools to review printed wafers, including wafers printed with FEMs, and to acquire more data associated with critical dimension measurements, for example. Finally, electrically testing FEM wafers can provide even more data that is suitable for defect identification and production yield analysis. To enable yield comparison, FEMs are printed on defective layers in full-flow production wafers, which facilitates comparisons with non-defective wafers. Such comparisons between empirically measured process windows and actual functional dies allows evaluation of the true process space when the lithography defect is combined with in-line process variation outside of the lithography module.
The printability of reticle CD errors depends not only on the defect size, but also defect location, defect shape, and the proximity of the defect to other features. The effect of the defects may also be influenced by product specific sensitivity and interaction with non-lithographic modules. Thus, employing a method that incorporates data from analyses including analyzing FEMs on full flow production wafers facilitates improving new product mask evaluation and improving defect impact yield analysis.
Analyzing FEMs printed on full flow production wafers in conjunction with reticle scans and printability simulation, flat wafer monitoring, critical dimension measurement and analysis facilitates collecting information in a plurality of ways. For reticles with more than one die per field, printing FEMs on actual full flow production wafers provides process sensitivity information at a functional level. As the position in the process window is varied across the wafer, dies can be compared to neighboring dies to scan for early yield roll off. At the bit level, the multi-tiered analysis approach facilitates identifying defect hot spots that may only occur under certain process conditions.
In accordance with an aspect of the present invention, a method for new product mask evaluation is provided. The method includes scanning a reticle and performing a printability simulation based, at least in part, on the reticle scanning. The method also includes performing defect scans on the printed wafers and flat wafer photo track monitoring. The method further includes performing critical dimension measuring and printing then analyzing one or more FEMs on full flow production wafers. The full flow production wafers are then subjected to end of line electrical testing to facilitate further defect detection, even at the bit level. Data gathered during the analysis phases of the method are then employed in performing a product yield analysis.
Another aspect of the present invention provides a data packet adapted to be transmitted between two or more processes, the data packet containing defect analysis information and product yield information produced by a method for new product mask evaluation, where the method includes reticle scanning, printability simulating based, at least in part, on the reticle scanning, defect scanning, flat wafer photo track monitoring, critical dimension measuring, full flow product focus exposure matrix monitoring, end of line electrical testing, defect detection, and product yield analysis.
Another aspect of the present invention provides a system for new product mask evaluation. The system includes a wafer defect analyzer, a reticle defect scanner operably coupled to the wafer defect analyzer, a printability simulator operably coupled to the wafer defect analyzer, a defect scanner operably coupled to the defect analyzer, a flat wafer monitor operably coupled to the defect analyzer, a critical dimension monitor operably coupled to the defect analyzer, a full flow product focus exposure matrix monitor operably coupled to the defect analyzer, and an end of line electrical tester operably coupled to the defect analyzer. In another aspect of the present invention, a yield predictor is operably coupled to the system described above in this paragraph.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.